1. Field of the Invention
The present invention relates to a method for manufacturing a nitride semiconductor substrate, and more particularly relates to a method for manufacturing a nitride semiconductor substrate with reduced dislocation and warpage.
2. Description of the Prior Art
It is known that nitride semiconductors, which are utilized to form LEDs, LDs, and other such light emitting elements or electronic devices, and which are expressed by the general formula InxAlyGa1-x-yN (0≦x, 0≦y, 0≦x+y≦1), are generally difficult to obtain in the form of bulk single crystals. Consequently, various research has been performed into growing a nitride semiconductor, with few dislocation defects, on a type of substrate different from the nitride semiconductor, such as sapphire, silicon carbide, spinel, or silicon (see, for example, Japanese Laid-Open Patent Applications H11-191657 and 2001-102307).
With this kind of method, to reduce the number of dislocation defects, patterns of various materials and shapes are formed on a different type of substrate, and a nitride semiconductor layer is grown over this pattern to form a (11-22) plane, and the growth is continued further to join the planes together.
However, dislocations occur at plane joints in a nitride semiconductor layer. For instance, when a striped pattern is used, there is a limit to how much dislocation defects can be reduced because dislocations are generated along the plane joints that occur linearly on the substrate.
Also, stress is produced within the nitride semiconductor layer because of the differences in the lattice constant, coefficient of thermal expansion, and so forth between the different type of substrate and the nitride semiconductor, which can cause the nitride semiconductor layer to be severed from the different type of substrate, leading to warping in a freestanding state.
Furthermore, as shown in FIGS. 6a and 6b, even when a pattern consisting of an arrangement of regular triangular or regular hexagonal openings is used (see, for example, Japanese Laid-Open Patent Application 2000-223417), there is still no reduction in the dislocation defects that arise through dislocation occurring along the plane joints of a nitride semiconductor layer (at vertex portions where sides of regular triangular or regular hexagon intersect).